A Protocol for Realtime Switched Communication in FPGA Clusters

Field programmable gate array (FPGA) devices typically have limited resources. This means that networks of FPGAs are required for implementing large-scale applications. Use of realtime communication channels can be used for reducing handshaking overhead in order to create high-performance networks. This paper describes a switched, real-time, link-level protocol and its implementation using Virtex-4 multigigabit transceivers. A prototype 4Gbps implementation of the protocol shows a per-hop latency and jitter of 310ns and 12.5ns, respectively, when endpoints run at a clock frequency of 100MHz. The prototype is also used to demonstrate the implementation of a jitter-free distributed global realtime clock that can be used for scheduling communication and computation of applications implemented using this cluster of FPGAs.